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IA82050 ASYNCHRONOUS SERIAL CONTROLLER FEATURES
* * * * * *
Data Sheet
As of Production Ver. 01
Form, Fit, and Function Compatible with the Intel(R) 82050 and 82510 Packaging options available: 28 Pin Plastic DIP and 28 Lead Plastic Leaded Chip Carrier Asynchronous Serial Channel Operation Separate Transmit and Receive FIFOs with Programmable Threshold Programmable Baud Rate Generators up to 288K Baud Special Protocol Features - Control Character Recognition - Auto Echo and Loopback Modes - 9-Bit Protocol Support - 5 to 9 Bit Character Format
The IA82050 is a "plug-and-play" drop-in replacement for the original IC. innovASIC produces replacement ICs using its MILESTM , or Managed IC Lifetime Extension System, cloning technology. This technology produces replacement ICs far more complex than "emulation" while ensuring they are compatible with the original IC. MILESTM captures the design of a clone so it can be produced even as silicon technology advances. MILESTM also verifies the clone against the original IC so that even the "undocumented features" are duplicated. This data sheet documents all necessary engineering information about the IA82050 including functional and I/O descriptions, electrical characteristics, and applicable timing.
IA82050 Package Pinout
IA82050
D4 D5 D6 D7 INT TXD VSS X2 or OUT2n X1 or CLK SCLK or RIn DSRn or TA or OUT0n DCDn or ICLK or OUT1n RXD CTSn (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (28) D3 D2 D1 D0 A2 A1 A0 VDD RDn WRn CSn RESET RTSn DTRn or TB DCDn or ICLK or OUT1n RESET CTSn RTSn RXD CSn INT TXD VSS X2 or OUT2n X1 or CLK SCLK or RIn DSRn or TA or OUT0n (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (25) (24) D0 A2 A1 A0 VDD RDn WRn (4) (3) (2) (1) (28) (27) (26) D7 D6 D5 D4 D3 D2 D1
28 Pin DIP
(27) (26) (25) (24) (23) (22) (21) (20) (19) (18) (17) (16) (15)
IA82050 28 Pin LCC
(23) (22) (21) (20) (19)
Copyright (c) 2001
ENG211010326-00 The End of ObsolescenceTM
DTRn or TB
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Page 1 of 11
IA82050 ASYNCHRONOUS SERIAL CONTROLLER DESCRIPTION
Data Sheet
As of Production Ver. 01
The IA82050 is an asynchronous serial controller that provides a CPU interface to one transmit and one receive channel. It is Form, Fit, and Function compatible with the Intel(R) 82050 and 82510. Configuration registers are used to control the serial channel, interrupts, and modes of operation. The CPU controls this device via address and data lines with read/write control. The CPU also uses this interface to read and write data to receive and transmit data through the serial channel. FIFOs and various serial modes can be used to help off-load the CPU from transmitting and receiving data. An interrupt line provides an indication to the CPU that the device requires servicing. The device can be configured for 8250A/16450 compatibility.
Functional Block Diagram
IA82050
A(2:0) D(7:0) RDn WRn CSn INT RESET RECEIVER RXD CTSn RTSn TIMING (Baud Rate Generators A & B, Clocking PIN CONFIGURATION DSRn or TA or OUT0n DCDn or ICLK or OUT1n DTRn or TB MODEM BUS INTERFACE (Reset Logic, Registers, Interrupt Generation, TRANSMITTER
TXD
CONFIG., STATUS, RXDATA TXDATA
X1 or CLK X2 or OUT2n SCLK or RIn
Copyright (c) 2001
ENG211010326-00 The End of ObsolescenceTM
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IA82050 ASYNCHRONOUS SERIAL CONTROLLER
Functional Overview
Transmitter
Data Sheet
As of Production Ver. 01
The Transmit function consists of a 4 x 11 bit FIFO, and a Transmit Engine. The 4 x 11 FIFO is configurable as any depth between one and four words inclusive. The transmit engine is responsible for reading the data out of the FIFO and placing it in the proper order on the TXD pin. The transmit engine is highly configurable to be compatible with numerous formats, including 16450 and 8250 modes of communication. Transmit Communication parameters that can be programmed include: * Parity modes * Stop Bits * Character Length * FIFO Depth * Clocking Options * RTS and CTS modes See the Register Description for more details. Receiver The Receiver function consists of a 4 x 11 configurable FIFO and a Receive Engine. The receive engine is responsible for sampling the data on the RXD input pin, formatting the data, and placing the data in the FIFO. The receive engine is highly configurable with parameters that include: * Parity modes * Stop Bits * Character Length * FIFO Depth * Clocking Options * Address Matching Options * Control Character Detection * RTS and CTS modes See the Register Description for more details. Bus Interface The Bus Interface is a simple interface that allows a micro-processor or micro-controller to read and write the IA82050 Registers. It consists of the following I/O lines: * A0, A1, A2 : 3 Bit Address * D0-D7 : 8 Bit Data * RDn: Active Low Read Enable * WRn: Active Low Write Enable * CSn: Active Low Chip Select * INT: Interrupt Output * RESET: Chip Reset
Copyright (c) 2001
ENG211010326-00 The End of ObsolescenceTM
innovASIC
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IA82050 ASYNCHRONOUS SERIAL CONTROLLER
Register Description
Register ACR0 ACR1 BACF BAH BAL BANK BBCF BBH BBL CLCF FLR FMD GER GIR_BANK GSR ICM IMD LCR LSR MCR MIE MSR PMD RCM RIE RMD RST RXDATA RXF TCM TMCR TMD TMIE TMST TXDATA TXF ADDR 111 101 001 001 000 010 011 001 000 000 100 001 001 010 111 111 100 011 101 100 100 101 110 110 100 101 110 111 101 000 001 110 011 011 110 011 000 001 Table 1 - IA82050 Register Summary Bank DLAB Mode 00 X R/W 10 X R/W 11 0 R/W 00 1 R/W 00 1 R/W X X W 11 X R/W 11 1 R/W 11 1 R/W 11 0 R/W 01 X R 10 X R/W 00 0 R/W X X R 01 X R 01 X W 10 X R/W 00 X R/W 00 X R/W 00 X R/W 01 X W 11 X R/W 00 X R/W 01 X R 11 X R/W 01 X W 10 X R/W 10 X R/W 01 X R 00 0 R 01 X 01 X R 01 X W 01 X W 10 X R/W 11 X R/W 01 X R 00 0 W 01 X 01 X W
Data Sheet
As of Production Ver. 01
Default 00000000 00000000 00000100 00000000 00000010 00000000 10000100 00000000 00000101 00000000 00000000 00000000 00000000 00000001 00010010 N/A 00001100 00000000 01100000 00000000 00001111 00000000 11111100 N/A 00011110 00000000 00000000 Unknown Unknown N/A N/A 00000000 00000000 00110000 N/A N/A
Copyright (c) 2001
ENG211010326-00 The End of ObsolescenceTM
innovASIC
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Page 4 of 11
IA82050 ASYNCHRONOUS SERIAL CONTROLLER AC/DC Parameters
Absolute maximum ratings:
Data Sheet
As of Production Ver. 01
Supply Voltage, VDD.....................................-0.3V to +6.0V Input Voltage, VIN.......................................-0.3V to VDD +0.3V Input Pin Current, IIN..................................10 mA, 25 C Operating Temperature Range..........................-40 C to +85C Ambient temperature under bias................................-40C to +85C * Storage temperature......................................................- 55C to +150C Lead Temperature........................................+300C, 10 sec. Power dissipation..............................................................155 mW, 125C, 25MHz, 15% Toggle
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. Operating the device beyond the conditions indicated in the "recommended operating conditions" section is not recommended. Operation at the "absolute maximum ratings" may adversely affect device reliability.
*
The input and output parametric values in section VII-B, parts 1, 2, and 3, are directly related to ambient temperature and DC supply voltage. A temperature or supply voltage range other than those specified in the Operating Conditions above will affect these values and part performance is not guaranteed by innovASIC.
Copyright (c) 2001
ENG211010326-00 The End of ObsolescenceTM
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Page 5 of 11
IA82050 ASYNCHRONOUS SERIAL CONTROLLER
DC Characteristics
Symbol VIL VIH1 VIH2 VOL VOH I LI I LO I CC I PU I STBY I OHR I OLR C IN C IO C XTAL Parameter Input Low Voltage Input High Voltage-Cerdip Input High Voltage-LCC Output Low Voltage Output High Voltage Input Leakage Current 3-State Leakage Current Power Supply Current Strapping Pullup Resistor Standby Supply Current RTSn, DTRn Strapping Current RTSn, DTRn Strapping Current Input Capacitance I/O Capacitance X1, X2 Load Notes (1) (1) (2) (2), (8) (3), (8) (4) (5) (6) (12) (9) (10) (11) (7) (7) N/A 5 6 6 -283 2.4 1 1 1.12 -137 100 1.92 Min -0.5 2.1 2.1 Max 0.7 VDD+.07 VDD+.07 0.4
Data Sheet
As of Production Ver. 01
Unit V V V V V A A mA/MHz A A mA mA pF pF pF
NOTES: 1. Does not apply to CLK/X1 pin, when configured as crystal oscillator input (X1). 2. @ I OL = 1.92 mA 3. @ I OH = 1.92 mA 4. 0< VIN < VCC . 5. 0.4V < VOUT < VCC - 0.4V
6. V DD = 5.5V, VIL = 0.7V (max), VIH = VDD - 0.7V (min), Typ. Val = 1.12 mA/MHz (Not Tested), Ext. 1X CLK, IOL = IOH = 0.
7. Freq. = 1MHz. 8. Does not apply to OUT2/X2 pin, when configured as crystal oscillator output (X2). 9. Freq. = 1MHz. But, input clock not running.
Static IDD current is exclusive of input/output drive requirements and is measured with the clocks stopped and all inputs tied to VDD or VSS, configured to draw minimum current.
10. Applies only during hardware reset for clock configuration options. Strapping current for logic HIGH. 11. Applies only during hardware reset for clock configuration options. Strapping current for logic LOW 12. Inputs (RTSn, DTRn, TB) with Pullups tested @ Vin = 0.0V VDD = 5.5V
Copyright (c) 2001
ENG211010326-00 The End of ObsolescenceTM
innovASIC
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Page 6 of 11
IA82050 ASYNCHRONOUS SERIAL CONTROLLER
AC Characteristics
Parameter CLK period CLK period CLK Low Time CLK High Time Min 54 ns 54 ns 25 ns 25 ns 250 ns 108 ns Max
Data Sheet
As of Production Ver. 01
Notes Divide by Two No Divide by
10 ns CLK Rise Time 10 ns CLK Fall Time CLK Rise Time CLK Fall Time Crystal Frequency Reset Width RTS/DTR Low Setup to Reset inactive RTS/DTR Low Hold after Reset inactive RDn Active Width Address/CSn Setup Time to RDn Active Address/CSn Hold after RDn Inactive RDn or WRn Inactive to Active Delay Data Out Float Delay after RDn Inactive WRn Active Width Address CSn Setup Time to WRn Active Address and CSn hold Time after WRn Data in Setup Time to WRn Inactive Data In Hold Time after WRn Inactive SCLK Period SCLK Period RXD Setup Time to SCLK High RXD Hold Time after SCLK High TXD Valid after SCLK Low TXD Delay after RXD
1 Mhz 8 * Clock Period 6 * Clock Period
15 ns 15 ns 20 Mhz
Divide by Two Measured between 0.3 * VDD and 0.7 * VDD Divide by Two Measured between 0.3 * VDD and 0.7 * VDD No Divide by No Divide by
Clock Period - 20 ns 2* clock period + 65 ns 7 ns 0 ns Clock Period + 15 ns 40 ns 2 * Clock Period + 15 ns 7 ns 0 ns 90 ns 12 ns 216 ns 3500 ns 250 ns 250 ns 170 ns 170 ns Remote Loopback 16x Clocking Mode 1x Clocking Mode
Copyright (c) 2001
ENG211010326-00 The End of ObsolescenceTM
innovASIC
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Page 7 of 11
IA82050 ASYNCHRONOUS SERIAL CONTROLLER Packaging Information
PLCC Package
1.22/1.07 2 PLCS
Data Sheet
As of Production Ver. 01
D
PIN 1 IDENTIFIER & ZONE
D1
E3
D3 TOP VIEW
E1
E
BOTTOM VIEW
.81 / .66
Symbol
LEAD COUNT
28 (in Millimeters) MIN 4.20 2.29 11.43 9.91 MAX 4.57 3.04 11.58 10.92 7.62 BSC 11.43 9.91 11.58 10.92 7.62 BSC 1.27 BSC 12.32 12.32 12.57 12.57
SEATING PLANE
A
A
A1
A1
D1
e .51 MIN.
.10
D2 D3 E1
.53 / .33
R 1.14 / .64
E2
D2 / E2 SIDE VIEW
E3 e D E
Copyright (c) 2001
ENG211010326-00 The End of ObsolescenceTM
innovASIC
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Page 8 of 11
IA82050 ASYNCHRONOUS SERIAL CONTROLLER
Data Sheet
As of Production Ver. 01
PDIP Package
TOP
E1
E
LEAD 1 IDENTIFIER
eA
1 LEAD COUNT DIRECTION
C
eB SIDE VIEW (WIDTH)
Lead Count
Symbol
D
A
28 (in Inches) MIN .015 .015 .050 .008 1.380 .580 .520 .100 TYP .580 .100 MIN .686 MAX .200 .020 .070 .012 1.470 .610 .560
A A1 B
A1
B1 C
L B B1 e
D E E1 e eA eB L B2 S
SIDE VIEW (LENGTH)
Copyright (c) 2001
ENG211010326-00 The End of ObsolescenceTM
innovASIC
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Page 9 of 11
IA82050 ASYNCHRONOUS SERIAL CONTROLLER
Data Sheet
As of Production Ver. 01
Ordering Information
Production Version 01
Order Number IA82050-PDW28I-01 IA82050-PDW28C-01 IA82050-PLC28I-01 IA82050-PLC28C-01 Environment Industrial Commercial Industrial Commercial Package Type 28 Lead Plastic DIP, 600 mil wide 28 Lead Plastic Leaded Chip Carrier
Copyright (c) 2001
ENG211010326-00 The End of ObsolescenceTM
innovASIC
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Page 10 of 11
IA82050 ASYNCHRONOUS SERIAL CONTROLLER ERRATA
Production Version 01
Data Sheet
As of Production Ver. 01
1. Issue: Issuing more than one command via the Receive Command register (RCM) may result in an unintended lock of the RX FIFO. Workaround: If multiple commands via the RCM are required, execute them individually. 2. Issue: In semi-automatic and automatic transmit mode, RTS will assert at the same time as the beginning of the start bit on TXD. If RTS is used to turn on the TXD line driver, the width of the start bit could be distorted. Workaround: Manual assertion of RTS and initiation of the transmit will avoid this issue.
Copyright (c) 2001
ENG211010326-00 The End of ObsolescenceTM
innovASIC
www.innovasic.com Customer Support: 1-888-824-4184
Page 11 of 11

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